An efficient VLSI architecture for HMM-based speech recognition
Jer Min Jou, Yeu-Horng Shiau, Chen-Jen Huang · 2002
A high speed and area-efficient VLSI architecture for HMM-based speech recognition is presented in this paper. It is designed by optimally applying the special property in speech recognition known as the left to right state transition model (LRM) and utilizing look-ahead pipelining techniques to break the recurrence of the speech recognition operations. In order to verify the proposed architecture, we have also designed and implemented it in a hardware prototype with Xilinx FPGAs. The simulation and emulation results show the recognition speed can achieve 25,000 words per second under 92% recognition rate with 500 references and 10,000 test patterns by 10 speakers.