Single chip H.32X multimedia communication processor with CIF 30f/s MPEG4/H.26X bi-directional codec
Noriyuki Minegishi, Nobuaki Motoyama, M. Takagi, Fuminobu Ogawa, Kouichi Shibata, N. Goda, K. Akiyoshi, Toshihisa Kamemaru, Kenichi Asano · European Solid-State Circuits Conference · 2001
A single multimedia communication chip suitable for plural products has been developed. This chip realizes real-time bi-directional encoding/decoding for CIF-resolution video at the frame rate of 30f/s, and meets H320, H.323, and H.324 standards. The chip is composed of a video-processing unit for H.26X standards, a DSP unit for speech codec and multiplex process, and a RISC unit for managing the whole chip. By careful study of task sharing for each processing unit and bus configuration, single chip solution can be achieved with reasonable operation speed and power consumption suitable for consumer products. This chip is being fabricated with a 4-metal 0.18µm CMOS technology and the chip area is 10.5 × 10.5 mm2with 1.5W power dissipation at 1.8V for internal, and 3.3V for I/O power supply.