A 90nm 512mb 166MHz multilevel cell flash memory with 1.5MByte/s programming
M. Taub, R. Bains, G. Barkley, Hernan Castro, G. Christensen, Sean Eilert, R. Fackenthal, H. Giduturi, M. Goldman, C. Haid, Rezaul Haque, Krishna K. Parat, Scott Peterson, A. Proescholdt, K. Ramamurthi, P. Ruby, B. Sivakumar, A. Smidt, Balaji Srinivasan, M. Szwarc · 2005
A 2b/cell flash memory in 90 nm triple-well CMOS technology achieves 1.5 MB/s programming and 166 MHz synchronous operation. The design features 2-row programming, optimized program control hardware, 3 transistor x-decoder with negative deselected rows and configurable output buffers. The die is 42.5 mm/sup 2/ with a cell size of 0.076 /spl mu/m/sup 2/.