HARDWARE IMPLEMENTATION OF EFFICIENT MODIFIED KARATSUBA MULTIPLIER USED IN ELLIPTIC CURVES
Sameh Shohdy, Ashraf B. El-Sisi, Nabil A. Ismail · 2010
The efficiency of the core Galois field arithmetic im-proves the performance of elliptic curve based public key cryptosystem implementation. This paper describes the design and implementation of a reconfigurable Ga-lois field multiplier, which is implemented using field pro-grammable gate arrays (FPGAs). The multiplier of Ga-lois field based on Karatsuba’s divide and conquer algo-rithm allows for reasonable speedup of the top-level public key algorithms. Binary Karatsuba multiplier is more effi-cient if it is truncated at n-bit multiplicand level and use an efficient classic multiplier algorithm. In these work three levels to truncate Binary Karatsuba algorithm (4 bits, 8 bits and 16 bits) are chosen showing that 8 bits is the best level for minimum number of slices and time delay to truncate Binary Karatsuba algorithm which is designed on an Xilinx VirtexE XCV2600 FPGA device. The VHDL hardware models are building using Xilinx ISE foundation software. This work is able to compute GF(2191) multiplication in 45.889 ns. experimental re-sults of comparing block and stream ciphers when used to secure VoIP in terms of end-to-end delay and subjec-tive quality of perceived voice.