Logical effort analysis of multi-port register file architectures
Neil Burgess · 2004
This paper introduces a simple delay model for register files based on the concepts of logical effort. The model takes the number and wordlength of registers, and the numbers of read and write ports as input parameters, and returns a delay estimate in FO4 ("fan-out of 4 inverters") units. The model shows that the number of registers has the greatest impact on the register file's read and write delays, whereas the wordlength of the registers and the number of ports have a smaller impact on the access delays.