Designing the M·CORE/sup TM/ M3 CPU architecture
Jeff Scott, Lea Hwang Lee, Albert Chin, Bill Moyer · 2003
The M/spl middot/CORE microRISC architecture has been developed to address the growing need for long battery life among today's portable applications. In this paper we present the architectural enhancements of the M3 processor the successor to the original M/spl middot/CORE M2 architecture. Specifically, we discuss the instruction buffer and pipeline enhancements, the branch prediction algorithm, branch folding for small program loops, the fast integer multiplier and several new instructions. We present performance comparisons between the M2 and M3 M/spl middot/CORE processors. Finally, we also discuss two system implementations utilizing the M/spl middot/CORE M3 processor.