Increasing vector processor pipeline efficiency with a thread-interleaved controller
Valeriu Codreanu, Lucian Petrică, R. Hobincu · International Conference on System Theory, Control and Computing · 2011
Vector processors are a fast and energy-efficient way of executing code with large amounts of data parallelism. Programmability has however been a difficult topic and has limited vector processors to a few niche applications. Recent advances in compiler auto-vectorization promise to make vector processors relevant for general-purpose computing. However, compiler-generated code is inefficient and makes poor use of vector resources, which are often the most area and power-consuming devices within a processing system. We propose adapting interleaved multi-threading, a proven technique for increasing pipeline efficiency of scalar processors, to improve utilization of vector resources, thereby providing gains in speed as well as potential reduction in energy consumption.