Selective data buffering module for unified hybrid storage system
Kihyun Park, Su-Kyung Yoon, Shin‐Dug Kim · 2015
A new design methodology is aggressively considered on conventional memory hierarchy structure because of newly emerging non-volatile memory technologies. This paper presents a unified single memory structure that merges existing main memory layer and secondary storage layer together. This structure eliminates conventional page swap operations causing significant performance degradation and supports fast program execution time. The unified single memory structure consists of a selective data buffering module and a hybrid array of PCM (phase change memory) and NAND Flash storage. This hybrid array of non-volatile memories is formed as a single memory-disk integrated storage space which can be logically divided into static and dynamic spaces. This research is to design a selective data buffering structure to reduce asymmetric read/write latencies and increase the lifetime of hybrid storage based on PCM and NAND Flash. The proposed structure is compared with the interfacing adapter structure of the memory-disk integrated system. Experimental results show that the hit rate of the selective data buffering structure increases by 90.5%, compared with the NVPO under the memory-disk integrated system [10], which shows 76.9% hit rate. The access latency is also improved by around 20.6%.