DRIBBLE-BACK REGISTERS: A TECHNIQUE FOR LATENCY TOLERANCE IN MULTIPROCESSORS
Vijayaraghavan Soundararajan · DSpace@MIT (Massachusetts Institute of Technology) · 1992
As parallel machines grow in scale and complexity, latency tolerance of synchroniza- tion faults and remote memory accesses becomes increasingly important. One method for tolerating this latency is by multithreading the processor and rapidly context switching between these threads. Fast context switching is most effective when the latencies being tolerated are short compared to the total run lengths of all the resident threads. If this condition is not met, it may become necessary to expend processor cycles to unload a blocked thread and load in a new one. This thesis presents the dribble-in, dribble-out register file, which facilitates fast context switching and the ability to hide the latency of loading and unloading context state. Through an analytical model and a simulation framework, we show that the dribble-in, dribble-out register file compares favorably against existing designs.