A Systolic FFT Architecture for Real Time FPGA Systems
Preston A. Jackson, Cy P. Chan, Jonathan Scalera, Charles M. Rader, M. Vai · Defense Technical Information Center (DTIC) · 2005
MIT Lincoln Laboratory has recently developed a new systolic FFT architecture for FPGAs. This architecture utilizes a parallel design to provide high throughput and excellent numerical accuracy. Using this design, an 8192-point real-time FFT, operating at 1.2 billion samples per second and performing 78 Gops with 70 dB of accuracy, fits on a single Xilinx Virtex II 8000.