Model Based Test Generation for Processor Verification
Yossi Lichtenstein, Yossi Malka, Aharon Aharon · UEA Digital Repository (University of East Anglia) · 1994
A few simple Expert-System techniques have been invaluable in developing a new test program generator for design verification of hardware processors. The new generator uses a formal declarative model of the processor architecture; it allows generation of test programs for a variety of processors without duplication of effort.