Fair cycle detection using description logic reasoning
Shoham Ben-David, Jeffrey Pound, Richard Trefler, Dmitry Tsarkov, Grant Weddell · Research Explorer (The University of Manchester) · 2009
Model checking ([11, 18], c.f.[10]) is a technique for verifying finite-state systems, that has been proven to be very effective in the verification of hardware and software pro-grams. In model checking, a model M, given as a set of state variables V and their next-state relations, is verified against a temporal logic formula ϕ. When ϕ holds on all