RISC and ASIC-the technologies of the nineties
D.J. Holzmann, Ulrich Mayer · 2003
The authors discuss the implementation of a reduced-instruction-set computing (RISC) microprocessor architecture in a fully integrated complex system solution. In benchmark studies, the RISC 32-b architecture offers higher performance than conventional 32-b microprocessors. This higher processing power is achieved by streamlining the instruction set to the most important and regularly used instructions, in an architecture which executes these instructions in one machine cycle while at the same time using a pipeline structure. RISC microprocessors are implemented typically in high-performance computers, workstations, and embedded-control real-time systems. The next generation of system implementation will combine RISC microprocessors and application-specific IC (ASIC) technology on one chip for easy transition to newer technologies as they arrive.>