A high performance memory and bus architecture for implementing 2D FFT on a SPMD machine
M. Cavadini, M. Wosnitza, M. Thaler, Gerhard Tröster · 2002
In this paper an optimized bus and memory architecture for the implementation of the two dimensional fast Fourier transform (FFT) on a single program multiple data architecture (SPMD) is presented. The data communication requirements of the FFT algorithm are discussed taking into account the bandwidth limitations imposed by the available memory devices. The proposed solution relies on the newest advances in DRAM storage technology. An implementation of the proposed architecture achieves 20 complex 2D FFTs/s on a 1024/spl times/1024 pixel image.