A 500 MHz 1.5 MB cache with on-chip CPU
J. Lachman, J. M. Hill · 2003
The access time, latency, and yield of embedded caches limit present generation processors to incorporate approximately 128 kB of memory. This 1.8 ns access time four-way-set-associative on-chip 1 MB data cache (D-cache) and 1.6 ns access time four-way-set-associative on-chip 0.5 MB instruction cache (I-cache) allow single-cycle access with up to three stores or loads executed every cycle. The caches communicate with the CPU over two 64 b data busses and a 128 b instruction bus running at the processor clock frequency of 500 MHz for 16 GB/s total effective bandwidth.