A multimedia 32 b RISC microprocessor with 16 Mb DRAM
Toshihisa Shimizu, J. Korematu, M. Satou, Hiroyuki Kondo, S. Iwata, Katsunori Sawai, Naoto Okumura, Koichi Ishimi, Y. Nakamoto, Masaki Kumanoya, Katsumi DOSAKA, Akira Yamazaki, Y. Ajioka, Hideo Tsubota, Yasuhiro Nunomura, T. Urabe, J. Hinata, Kazunori Saitoh · 2002
This 32 b microprocessor with on-chip 2 MB DRAM is for multimedia applications that require a low-power embedded microprocessor and large memory. Using a typical 0.45 /spl mu/m DRAM process, double-metal CMOS technology, this chip integrates 17 M transistors in 19.9/spl times/7.7 mm/sup 2/. It consists of a 32 b RISC CPU, a 32 b/spl times/16 b multiply accumulator (MAC), a 2 MB DRAM, a 2 kB cache, an external bus interface unit (BIU), and control units. The CPU, DRAM, cache and BIU are connected with a single 128 b internal bus. At 66 MHz, the bus transfers a 128 b data line between the CPU and the cache in one cycle, and between CPU and DRAM in 5 cycles. The external bus is 16 b wide and operates at 16.67 MHz.