A verification technique for communication hardware and its application to a real chip design
Masahiro Fujita, Bu Chen, M. Yamazaki · 2002
We present an abstraction technique for formal hardware verification by which we can verify realistic site chips for communication systems. The abstraction method makes it possible to abstract away datapaths relating to the packets format of communicating data. We successfully applied it to verification of the buffer control operations in one of our communication chips in parallel to the design process.