Reconfigurable FPGA processor
Andreas Romer, Rolf Enzler, Didier Cottet, Gerhard Tröster · Repository for Publications and Research Data (ETH Zurich) · 2000
Progress in the FPGA technology have made partial reconfigurable devices appear on the market.The device size is also getting larger pushed by the progress in CMOS technology.There are already devices on the market that have reached the one million gate equivalent, thus allowing to map whole processors on FPGAs.In this report a concept of a dynamic reconfigurable processor is being introduced that includes a very simple accumulator processor.It can allocate functional units through a reconfiguration process into the reconfigurable part, in order to be able to execute an instruction.The concept is validated with an implementation on the Virtex device of Xilinx.The Virtex and the XC6200 devices of Xilinx are described in detail, and their design flows are explained.A proposal is made for a design flow to create a locally constraint partial reconfiguration for the Virtex.An in VHDL written implementation of the processor onto the Virtex resulted in a clock frequency of 55 MHz with only 300 CLB slices used of a Virtex device.This is less than a tenth of a XCV300 and equals to about 5440 gate equivalents.