Logic and system design for low power consumption
Vivek Tiwari · 1996
Power consumption has emerged as one of the most important system design constraints. This has been motivated by the increasing popularity of energy-limited mobile systems and the increasing cooling and packaging costs associated with higher heat dissipation. Recent years have also seen a growing role of software in the design of electronic systems. A large fraction of applications are now being designed as embedded systems, where the functionality is partitioned between hardware and software. Given the above trends, there is a clear need to analyze and optimize power consumption for both the hardware as well as software design components. For the hardware component, a big thrust in the research community has been to extend traditional computer aided design (CAD) techniques to a new dimension--power. Part of this thesis focuses on a specific problem in this domain--technology mapping during logic synthesis, i.e., the process of selecting gates from a given library during automated logic design. Models and algorithms are developed to consider power as the optimization metric during the technology mapping process. The hardware design technique that has proven to be one of the most successful for reducing power in commercial systems is dynamic power management. This thesis attempts to increase the scope of this technique by pushing it down to lower levels of the design process. A technique to automatically apply principles of power management to logic level synthesis/design is presented. The ideas can be extended to the register transfer and higher levels. In order to understand this aspect further, the application of dynamic power management to a complete microprocessor design is studied. In contrast to the hardware component, the power consumption in the software part of systems has thus far been very poorly understood. A major thrust of this thesis has been to overcome this deficiency. A measurement based instruction-level power analysis methodology has been developed to model the power cost of software. Results from its application to three commercial microprocessors are presented. The ability to evaluate the power cost of software is then used to search the design space in software power optimization.