A massively scaleable decoder architecture for low-density parity-check codes
A. Selvarathinam, G.S. Choi, Krishna R. Narayanan, A. Prabhakar, Euncheol Kim · 2003
A massively scalable architecture for decoding low-density parity-check codes is presented in this paper. This novel architecture uses hardware scaling and memory partitioning to achieve a throughput of 100 Gbps. Simulation results show that this throughput is achieved without significant bit-error performance degradation.