A 100MIPS Ps, 64b Superscalar Microprocessor With DSP Enhancements
R. Talmud, O. Oz, M. Beck, Shmuel Shalem, Assaf Shacham, A. Mizrachi, Y. Afek · 1991
This microprocessor provides high performance at moderate system cost, and is targeted for computation-intensive, embedded control applications. It meets the needs of performance- driven applications, by implementing a RISC architecture and utilizing superscalar design techniques. The microprocessor incorporates two independent integer units, a floating- point unit, instruction and data caches, and a 64b bus. It also incorporates DSP enhancements. The two integer units and the floating-point unit can execute instructions in parallel to provide either two integer operations, or one integer and one floating-point operation per clock cycle. At 50MHz, the microprocessor achieves 112,000 Dhrystones/s, 20MFLOPS in the double-precision Linpack inner loop, 1024-point integer FIT in 1498µs and 1024-point floating-point FFTin 1025µs. To minimize cost, the microprocessor uses clocking which allows the bus to operate at half the frequency of the internal clock. Half-frequency bus operation allows for a conventional memory system design at 25MHz clock while the microprocessor runs internally at 50MHz. To further reduce cost, a direct memory access (DMA) controller, an interrupt control unit (ICU) and a timer are integrated on-chip. (Figure 1) The die is 13xl3mm, using a 0.8µm double-metal CMOS process.