FPGA implementation of FIR filter using M-bit parallel distributed arithmetic
Shiann‐Shiun Jeng, Hsing-Chen Lin, Shu‐Ming Chang · 2006
An efficient architecture for a FPGA symmetry FIR filter is proposed that employs M-bit parallel-distributed arithmetic (M-bit PDA). The partial product is pre-calculated and saved into the distributed RAM. This eliminates the large amount of logic needed to compute multiplication results. The proposed architecture consumes less area and offers higher speed operation because the multiplier is omitted. Altera APEX20KE is used as a target device. Thus, the proposed architecture has high processing speed and small area