The RTL Binding and Mapping Approach of VHDL High-Level Synthesis System HLS/BIT
颜宗福, 刘明业 · 1996
This paper describes a VHDL high-level synthesis system HLS/BIT with emphasis on its register-transfer level(RTL)binding and technology mapping subsystem.In more detail,the component instantiation mechanism and the knowledge-driven approach to RTL technology mapping are also presented.