Power-efficient VLSI implementation of bitstream parsing in H.264/AVC decoder
Ke Xu, Chiu‐Sing Choy, Cheong-Fat Chan, Kong-pong Pun · 2006
In this paper, we propose a power-efficient bitstream parsing for H.264/AVC baseline profile decoding. It parses the input bitstream syntaxes and controls the following decoding steps. Various power reduction techniques, such as data-driven based on statistic results, nonuniform partition, precomputation, guarded evaluation, hierarchical FSM decomposition, clock gating etc., have been adopted in our design. The VLSI implementation results show that under UMC130nm technology with 1.08V supply voltage, the core power consumption is only 1.98mW@20MHz for real-time decoding. Total hardware costs are 49k gates and 1.2 /spl times/ 1.2mm/sup 2/ chip area. The power-efficient and real-time features make our design ideal for low-power video transmission applications such as mobile phone and PDA where video quality is often traded off for energy.