A Fully Testable Single-Chip 32-Bits Multi-formats Floating Point Processor
Philippe Bornes, Anne Derieux, J. A. Francois, C. Manga, Habib Mehrez, Gérard L. M. NOGUEZ, K. Shamsa · European Solid-State Circuits Conference · 1990
This article describes the architecture and design of a fully testable floating point processor. It performs 32-bits floating point arithmetic operations (addition, subtraction and multiplication) and it also performs integer-to-floating point, floating point-to-integer and inter-format conversions using either IEEE-P745 10.0, DEC-VAX or a two's complement format To enhance performances, the processor includes a 16×32 bits double access RAM. Designed for CMOS hard technologies, the chip contains about 55000 transistors in 90 mm2 and performs a hole operation in less than 200 ns.