A SystemC Based System On Chip Modelling and Design Methodology
Yves Vanderperren, Marc Pauwels, Wim Dehaene, Ates Berna, Fatma ÖZDEMİR · Kluwer Academic Publishers eBooks · 2006
This paper describes aspects of the process and methodologies used in the development of a complex System On Chip. SystemC played a key role in supporting the technical work based on a defined refinement process from early architectural modelling to detailed cycle accurate modelling elements which enabled early co-simulation and validation work. In addition to SystemC, significant use was made of the Unified Modelling Language, and process and methodology associated with it, to provide visual, structured models and documentation of the architecture and design as it developed. These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.