An On-chip Multiprocessor Microprocessor with Shared MMU and Cache
Yong–Hwan Lee, Wookyeong Jeong, Sang-Jun An, Yong-Surk Lee · Journal of Electrical Engineering and Information Science · 1997
A multiprocessor microprocessor named SMPC(scaleable multiprocessor chip) that contains two IU (integer unit) is presented in this paper. It can execute multiple instructions from several tasks exploiting task-level parallelism that is free from instruction dependencies, and provide high performance and throughput on both single program and multiprogramming environments. The IU is a 32-bit scalar processor especially designed to boost up the performance of string manipulations which are frequently used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. The SMPC is implemented in VLSI circuit by custom design and automated design tools.