Communications Processor Architecture: A Microprocessor Design
John Amos Boles, L.R. Carlson · 2005
The Communications Processor Architecture is implemented In tbe Sperry Univac r DCP/40 /spl sub (1), and is targeted towards high performance secure operation and network functionality. The architecture supports the utilization of large scale integration, microprocessors and microprogramming in every module. In addition to providing functionality and performance in the communications environment, the DCP/40 provides excellent general purpose processing capability. increased performance is achieved through advanced components and functional distribution of tasks among the various processing elements. Security and integrity is attained through address and queue access protection. As a unique feature of the architecture, all I/0 is treated in common whether it drives peripheral devices or communications lines. This technique simplifies software as well as hardware design.