10 Gbit/s Throughput Telecommunication Circuits in CMOS
A. Edman, B.G.R. Rudberg · European Solid-State Circuits Conference · 1996
We present an architecture suitable for implementing the processing parts of high throughput telecommunication terminal equipment, in standard CMOS. A first testchip has been designed in 0.8 ?m CMOS and successfully tested. It contains some critical processing parts of an SDH-regenerator. The chip process a throughput of 10 Gbit/s and is fully clocked at 622 MHz.