A 500 MHz 64b RISC CPU with 1.5 MB on-chip cache
Peter D. Barnes · 2003
A 64b quad issue PA-RISC microprocessor with full out-of-order execution is migrated from 0.5 /spl mu/m CMOS into an advanced 0.25 /spl mu/m CMOS process. Features include an integrated on-chip 1.0 MB L1 data and 0.5 MB L1 instruction caches and a dual-voltage memory bus interface. The processor incorporates 116 M transistors on a 21.3/spl times/22 mm/sup 2/ die running in excess of 50O MHz at 85/spl deg/C and 2.0 V and delivering greater than 32 SPECint95 and greater than 52 SPECfp95 in a 440 MHz product configuration.