CVT-FERT: automatic generator of analytical faults at RT-level from electrical and topological descriptions
M. Melgara, Maurizio Paolini, Roberto Roncella, S. Morpurgo · 1984
This paper describes CVT-FERT, a physical fault simulator. The program takes as input a circuit electrical description extracted from the layout and a list of physical faults. Mter fault collapsing. the logical flow table of both the fault-free and each faulty version of the circuit are computed. The circuit is modeled as a network of interconnected hazard-free blocks. handled by a dedicated simulator; each block is described by logical and timing information. collected by electrical simulation. The flow table construction is performed in three steps: individuation of the network potential memory nodes. identification of the steady states associated with each input vector and verification of every critical transition. The flow tables can be used as a meaningful fault model in RT-level fault simulation.