Cost-effectively improving life endurance of MLC NAND flash SSDs via hierarchical data redundancy and heterogeneous flash memory
Shishi Tan, Ruirong Yu, Shenggang Wan, Qiang Cao · 2015
As an alternative to conventional spinning HDDs, MLC NAND flash memory based SSDs suffer from a low life endurance. To cost-effectively address this problem, we propose integrating both Hierarchical data redundancy and Heterogeneous flash memory techniques into those SSDs, named as H2-SSD. By deploying across-chips data redundancy in addition to the conventional in-page ECCs, the error correction capacity of H2-SSD can be dramatically enhanced. As a result, the life endurance can be significantly improved. Furthermore, an extra small sized SLC chip is deployed in H2-SSD to store the across-chips parity. Due to the high Program/Erase performance and life endurance of that SLC chip, the degradation of I/O performance induced by the hierarchical data redundancy will be slight in most cases, even under a strict synchronous parity update strategy. Both quantitatively analysis and trace-driven simulation are conducted to evaluate the effectiveness of H2-SSD. The results demonstrate that H2-SSD outperforms the conventional SSDs in the maximum Program/Erase cycles by 23% to 178% and suffer from a less than 10% degradation of I/O performance under most cases.