A single chip Lempel-Ziv data compressor
B.W.Y. Wei, R. Tarver, J.-S. Kim, K. Ng · 1993 IEEE International Symposium on Circuits and Systems · 2002
A single-chip implementation of the Lempel-Ziv adaptive data compression algorithm in 1.2-/spl mu/m CMOS technology is described. The chip uses 2K-byte on-chip content addressable memory (CAM)/SRAM for storing the most recent input characters to which the incoming string is compared against and referenced. It performs compression or decompression on byte-oriented input data at a data rate of one byte per clock cycle, except when one out of every 33 cycles is used to update the string dictionary.>