A wire-delay scalable microprocessor architecture for high performance systems
S.W. Keckler, Douglas C. Burger, Charles R. Moore, Ramadass Nagarajan, Karthikeyan Sankaralingam, Vikas Kumar Agarwal, M.S. Hrishikesh, Nitya Ranganathan, Premkishore Shivakumar · 2003
This scalable processor architecture consists of chained ALUs to minimize the physical distance between dependent instructions, thus mitigating the effect of long on-chip wire delays. Simulation studies demonstrate 1.3-15/spl times/ more instructions per clock than conventional superscalar architectures.