Compiler Scheduling for STA-Processors
Gordon Cichon, Pablo Robelly, Hendrik Seidel, Marcus J. Bronzel, Gerhard Fettweis · 2004
This paper presents an adaptation of the list scheduling algorithm to generate code for processors of the Synchronous Transfer Architecture (STA) by applying techniques known from RISC and TTA. The proposed scheduling approach is based on informed, deterministic algorithms that can be implemented run-time efficiently. Although the presented compiler prototype does not generate optimized code, it provides a proof-of-concept of the feasibility of the proposed compiler architecture.