Design of B(x)/sup -1/mod F(x) for high-speed communications
Sungsoo Choi, Kwan‐Ho Kim, Kiseon Kim · 2004
In designing high-speed communications, the smallest functional unit like arithmetic, B(x)/sup -1/mod F(x), should be carefully designed and optimized well to improve the overall performance. To do this, we study two variations that is, square-first and multiply-first type operations - for the repetition-operation of the numerical formula, AB/sup 2/. From these two variations, we propose m-bit parallel semi-systolic architectures for GF(2/sup m/) inversion. When we compared performance of them with those of different inversion architectures based on a normal power-sum operation, based on small grain of special power-sum operation, and based on a Euclidean algorithm, performance of the proposed one, which is based on small grain of special power-sum operation, is the best for the purpose of high-speed applications. When we implement a simplified 8-bit parallel semi-systolic architecture for square-first inversion circuit over GF(2/sup m/) by using 0.25 /spl mu/W CMOS library, it has 2495 equivalent logic-gates, 1848 1-bit latches, and the latency is 56 and the clock-rate is up to 580 MHz at 100% throughput.