An image retrieval system using FPGAs
Koji Nakano, Etsuko Takamichi · Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003. · 2003
The main contribution of this paper is to present an image retrieval system using FPGAs. Given a template image T and a database of a number of images I/sub 1/, I/sub 2/,..., our system lists all images that contain a subimage similar to T. More specifically, a hardware generator in our system creates the Verilog HDL source of a hardware that determines whether I/sub i/ has a similar subimage to T for any image Ii and a particular template T. The created Verilog HDL source is embed in an FPGA using the design tool provided by the FPGA vendor. Since the hardware embedded in the FPGA is designed for a particular template T, it is an instance-specific hardware that allows us to achieve extreme acceleration. We evaluate the performance of our image matching hardware using a PCI-connected Xilinx FPGA and a tinting analyzer. Since the generated hardware attains up to 3000 speedup factor over the software solution, our approach is promising.