Implementation of a fully parallel Kohonen map: a mixed analog digital approach
Vinesha Peiris, B. Hochet, Michel J. Declercq · 2002
This paper describes the CMOS implementation of a digitally behaving Kohonen map. Although input values and synaptic weights are quantized, the basic blocks are implemented using digital or analog techniques where best suited, combined with efficient information encoding. This has lead the authors to the design of a modular 4/spl times/4 Kohonen neuron chip that may be cascaded in order to realize large size fully parallel Kohonen maps.>