A 1024-BIT IMPLEMENTATION OF THE FASTER MONTGOMERY MULTIPLIER USING VHDL
David Narh Amanor · The African review of physics · 2009
This paper presents a 1024-bit implementation of the recently proposed Faster Montgomery algorithm for performing modular multiplication. The object of this paper is to show how complex microelectronic systems or architectures could be modelled, simulated, synthesized and emulated on an FPGA (or fabricated as an ASIC) through the use of the industry standard language VHDL (IEEE-1076) as the design entry. The implementation used higher levels of abstraction to partition the complex design into subsystems or components. These components were implemented as independent functional blocks before being wired together to construct the Faster Montgomery architecture. The VHDL implementation was simulated and synthesized for a Xilinx Virtex FPGA. But, the code could also be used as the design entry for an ASIC. The work concludes by specifying the hardware requirements needed for the fabrication of the Faster Montgomery architecture.