Design of a cell library for formal high level synthesis
Sadiq M. Sait, Masad-ul-Hasan, Khaled M. Elleithy · 2002
In this paper we present a complete design and implementation of a CMOS cell library which supports a formal high level synthesis framework. The library contains the logic level models and VLSI layouts of all primitive functions of the realization specification language (RSL) as well as some commonly used functions which are also built using these basic functions. Modular design methodology is employed to support the expandibility of the basic cells. Example of a formal matrix-matrix multiplier is presented to illustrate the application of the cell library.>