First-generation MAJC dual microprocessor
A. Kowalczyk, Victor Adler, C. Amir, F. Chiu, Choon Chug, W. De Lange, Scott Dubler, Yuefei Ge, Subhendra Ghosh, Tan Hoang, R. Hu, Baoqing Huang, Shashi Kant, Y.S. Kao, Cong Khieu, Suresh Kumar, Chung Lau, Lan Lee, A. Liebermensch, Xin Liu · 2002
The MAJC 5200 is a dual 32b microprocessor system-on-a-chip, utilizing 0.22 /spl mu/m CMOS with all-Cu interconnect. Two CPUs, delivering GGFLOPS and 13GOPS at 500 MHz, are tightly coupled through a shared, coherent, 4-way set associative 16 KB data cache, and an on-chip 4 GB/s switch. Each CPU is a 4-issue VLIW engine.