High-Level Synthesis of Digital Circuits
Giovanni De Micheli · Advances in computers · 1993
This chapter discusses state-of-the-art in the high-level synthesis of digital circuits, the success achieved by high-level synthesis, and the present difficulties. It mentions that high-level modeling is done by means of hardware description languages (HDLs). The lack of standardization of HDLs suitable for synthesis has been a major impediment in the diffusion of high-level synthesis. The chapter discusses modeling issues with particular reference to abstract circuit models, based on graphs that can serve as a common basis for synthesis and that decouple synthesis and optimization from the particular features of any given language. Sequel circuit models are discussed at both the functional and logic abstraction levels with behavioral and structural flavors. The chapter describes scheduling, resource binding, and control synthesis. Structural synthesis and the related tasks are described as applied to non-pipelined circuits, and extensions to pipelined models are reported. The chapter concludes by giving a short history of high-level synthesis and by describing and comparing high-level synthesis.