Compression/decompression DRAM for unified memory systems: a 16 Mb, 200 MHz, 90% to 50% graphics-bandwidth reduction prototype
Y. Yabe, Yoshiharu Aimoto, Masato Motomura, T. Takizawa, T. Miyamoto, Takahiro Iwasaki, Y. Nakazawa, T. Fujii, Mototsugu Hamada, N. Nagai, M. Yamashina · 2002
Describes a unified memory system containing CompressDRAMs. The system is based on a Synclink-type packet-oriented DRAM architecture. CompressDRAMs are connected along the main memory bus, just as other conventional DRAMs are. A frame buffer is allocated on a CompressDRAM, and the graphics data is transferred in compressed form from/to the frame buffer. Here the memory bus consists of unidirectional command link and bi-directional data link, both at 200MHz, double data rate. A 40b request packet is issued from a memory/graphics controller to a target DRAM or CompressDRAM using 10b CA of Command Link, while a variable length data packet is transmitted over 16b DQ of Data Link (800MB/s peak bandwidth). A unidirectional READY signal is newly introduced to synchronize the controller and the CompressDRAMs.