Configuring multiple boundary scan chains for board testing
Yoon-Hwa Choi, Chul Kim, E. Jung · 2002
In a board level design with boundary scans, each chip on a board can be tested by loading test vectors and collecting responses through a boundary scan chain. Since the boundary scan may serialize the test process, the overall test time can be reduced if multiple boundary scan chains are used. In that case the test time depends on how the boundary scan chips are connected into multiple chains. In this paper, we present a technique for configuring multiple boundary scan chains to minimize the test time for boundary scan chips on a board.