Parallel Processor Algorithm for Variable Block-Size Computation at Low Bitrates
Lauri Koskinen, Kari A. I. Halonen, A. Paasio · 2005
A two step algorithm for H.264 motion estimation variable block size selection is presented. The method is implementable in analog parallel processors in connection with the sensor arrays of mobile terminals. The target of such processor arrays is low-power, real-time video encoding of mobile terminal low bitrate conversational services. The algorithm indicates areas of active motion and gradients within each frame. These are then used to allocate block-sizes, skip modes and early termination of the motion estimation. The algorithm achieves higher performance when compared to motion estimation using only 16/spl times/16 sized blocks and, for low bitrates, gives comparable performance when compared to Lagrange optimization.