Approximate Algorithms for Identifying Minima on Min-Sum LDPC Decoders and Their Hardware Implementation
Ioannis Tsatsaragkos, Vassilis Paliouras · IEEE Transactions on Circuits & Systems II Express Briefs · 2015
This brief introduces algorithms and corresponding circuits that identify minimum values among a set of incoming messages. The problem of finding two minima in a set of messages is approximated by the different problem of finding the minimum of all messages in the set and the second minimum among a subset of the messages. This approximation is here shown to be suitable for hardware low-density parity-check decoders that implement a min-sum (MS) decoding algorithm and its variations. The introduced approximation simplifies the operation performed in a check-node processor and leads to hardware reduction. The proposed schemes outperform other state-of-the-art simplified MS architectures, approaching the error-corrective performance of the normalized MS decoding algorithm.