Performance trade-off of DCT architectures in Xilinx FPGAs
Dhanesh Kumar, Keshab K. Parhi · 2003
This paper presents the performance trade-offs among a class of three different 8-point 1-D discrete cosine transform (DCT) architectures implemented in Xilinx FPGAs. The architectures chosen for implementation are the distributed arithmetic (DA) architecture (with digit sizes 1 and 3), digit-serial flow graph (DSFG) architectures (with digit sizes 2, 3 and 6) and systolic architecture. The experiments show that the DA is the best architecture in terms of area, speed and latency while the systolic architecture is the worst. The 3-bit serial DA architecture has 85% better area*delay product, 24% lower clock energy per computation and 90% less latency as compared to the systolic design and it provides a HDTV throughput of 111 MPix/sec. The performance of the DSFG designs vary with digit-size. The 2-bit and 3-bit DSFG architectures have a poorer performance as compared to the DA architectures in that throughput range. However 6-bit DSFG comes quite close to 3-bit DA architecture. It has 83% better area*delay product, 13% lower clock energy per computation and 80% less latency as compared to the systolic architecture and provides a throughput of 163 MPix/sec. Another interesting observation is the dominance of route delays which form approximately 50% of the critical path delays.