Layout, performance and power trade-offs in mesh-based network-on chip architectures.
Dinesh Pamunuwa, Johnny Öberg, Li‐Rong Zheng, Mikael Millberg, Axel Jantsch, Hannu Tenhunen · 2003
On-chip packet-switched networks have been proposed for future giga-scale integration in the nanometre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout and wiring strategies based on full-swing CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off. 1.