An efficient architecture for an improved watershed algorithm and its FPGA implementation
C. Rambabu, L. Chakrabarti, A. Mahanta · 2003
This paper proposes a fast watershed algorithm derived from Meyer's simulated flooding based algorithm. The parallel processing adopted in conditional neighborhood comparisons for processing 3/spl times/3 pixels in one process leads to reduced computational complexity compared to Meyer's algorithm. The proposed algorithm has been implemented in an Xilinx FPGA environment.