An out-of-order three-way superscalar multimedia floating-point unit
A. Scherer, Michael Golden, N. Juffa, S. Meier, Stuart F. Oberman, Hamid Partovi, F. Weber · 2003
The AMD-K7/sup TM/ floating point unit is implemented as an out-of-order coprocessor responsible for executing all x86 FPU, MMX/sup TM/, and AMD 3DNoW!/sup TM/ instructions. The FPU interfaces to the AMD-K7 core, which sends it instructions, load data, and guides the retirement of instructions. The FPU sends store data and completion status back to the core. The FPU contains 2.4 M transistors on a 10.5/spl times/2.6 mm/sup 2/ die in a 0.25 /spl mu/m process. A micrograph of the FPU is shown.